网络与信息安全学报 ›› 2021, Vol. 7 ›› Issue (2): 64-76.doi: 10.11959/j.issn.2096-109x.2021026

• 专题:集成电路硬件安全 • 上一篇    

紧凑的Aigis-sig数字签名方案软硬件协同实现方法

周朕1,2, 何德彪1,2, 罗敏1,2, 李莉1,2   

  1. 1 空天信息安全与可信计算教育部重点实验室,湖北 武汉 430072
    2 武汉大学国家网络安全学院,湖北 武汉 430072
  • 修回日期:2021-01-09 出版日期:2021-04-01 发布日期:2021-04-01
  • 作者简介:周朕(1996- ),男,安徽亳州人,武汉大学硕士生,主要研究方向为后量子密码、密码算法设计实现。
    何德彪(1980- ),男,山东阳谷人,武汉大学教授、博士生导师,主要研究方向为密码学、区块链安全等。
    罗敏(1974- ),男,湖北武汉人,武汉大学副教授,主要研究方向为密码学、区块链安全等。
    李莉(1976- ),女,湖北武汉人,武汉大学副教授,主要研究方向为密码学、区块链安全等。
  • 基金资助:
    国家自然科学基金(61972294);国家自然科学基金(61932016)

Compact software/hardware co-design and implementation method of Aigis-sig digital signature scheme

Zhen ZHOU1,2, Debiao HE1,2, Min LUO1,2, Li LI1,2   

  1. 1 Key Laboratory of Aerospace Information Security and Trusted Computing, Ministry of Education, Wuhan 430072, China
    2 China School of Cyber Science and Engineering, Wuhan University, Wuhan 430072, China
  • Revised:2021-01-09 Online:2021-04-01 Published:2021-04-01
  • Supported by:
    The National Natural Science Foundation of China(61972294);The National Natural Science Foundation of China(61932016)

摘要:

基于理想格构造的 Aigis-sig 数字签名方案具有实现效率高、签名长度短、抗量子攻击等优势。针对Aigis-sig方案,构造了一种改进的模乘计算元件,设计了一种基于快速数论变换(NTT)算法实现环上多项式运算的紧凑硬件架构;同时以此架构为基础,提出了Aigis-sig数字签名方案的FPGA软硬件协同实现方法。实验表明,在Xilinx Zynq-7000 SoC平台上,CPU频率和硬件频率分别设置为666.66 MHz和150 MHz时,该实现方案相较于纯软件实现,签名阶段和验签阶段分别取得约26%和17%的性能提升。

关键词: 后量子密码, 数字签名, Aigis-sig, 现场可编程逻辑门阵列, 快速数论变换

Abstract:

Digital signature scheme Aigis-sig, constructed on ideal lattice, takes the advantages of high efficiency, short signature length and resistant to quantum attack, etc.An optimized modular multiplication arithmetic component was constructed and a compact hardware architecture for polynomial operation over a ring based on number theory transformation (NTT) algorithm for Aigis-sig was designed.Besides, based on this architecture, software/hardware co-design and implementation for Aigis-sig scheme on FPGA platform in cryptography was proposed.Experimental results show that the speed of signature phase and verification phase are increased by about 26% and 17% respectively, compared with the pure software implementation on Xilinx Zynq-7000 SoC platform when CPU clock frequency and hardware clock frequency are set as 666.66MHz and 150 MHz respectively.

Key words: post-quantum cryptography, digital signature, Aigis-sig, FPGA, number theory transformation

中图分类号: 

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