基于FPGA的新型强弱混合型PUF电路设计

doi:10.11959/j.issn.2096-109x.2021028

网络与信息安全学报 ›› 2021, Vol. 7 ›› Issue (2): 94-103.doi: 10.11959/j.issn.2096-109x.2021028

• 专题：集成电路硬件安全 • 上一篇下一篇

基于FPGA的新型强弱混合型PUF电路设计

连佳娜¹^,², 汪鹏君¹, 李刚¹, 马雪娇¹^,³, 翟官宝¹

¹ 温州大学电气与电子工程学院，浙江温州 325000
² 温州大学计算机与人工智能学院，浙江温州 325000
³ 温州大学瓯江学院，浙江温州 325000)

修回日期:2021-02-22 出版日期:2021-04-15 发布日期:2021-04-01
作者简介:连佳娜（1996- ），女，浙江绍兴人，温州大学硕士生，主要研究方向为物理不可克隆函数攻击与防御。
汪鹏君（1966- ），男，浙江宁波人，温州大学教授、博士生导师，主要研究方向为低功耗、高信息密度集成电路理论和设计技术、电路设计综合和优化技术、安全芯片理论和设计技术。
李刚（1988- ），男，陕西汉中人，温州大学讲师，主要研究方向为密码芯片攻击和防御理论及其VLSI实现、存储计算、数字电路逻辑综合与优化。
马雪娇（1991- ），女，河北秦皇岛人，主要研究方向为数字电路逻辑综合与优化、硬件混淆技术。
翟官宝（1998- ），男，浙江衢州人，温州大学硕士生，主要研究方向为物理不可克隆函数攻击与防御。
基金资助:
国家重点研发计划(2018YFB2202100);国家自然科学基金(61874078);国家自然科学基金(61904125);温州市基础性科研项目(G20190006);温州市基础性科研项目(G20190003)

Novel hybrid strong and weak PUF design based on FPGA

Jiana LIAN¹^,², Pengjun WANG¹, Gang LI¹, Xuejiao MA¹^,³, Guanbao ZHAI¹

¹ College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325000, China
² College of Computer Science and Artificial Intelligence, Wenzhou University, Wenzhou 325000, China
³ Oujiang College, Wenzhou University, Wenzhou 325000, China

Revised:2021-02-22 Online:2021-04-15 Published:2021-04-01
Supported by:
The National Key R＆D Program of China(2018YFB2202100);The National Natural Science Foundation of China(61874078);The National Natural Science Foundation of China(61904125);Basic Scientific Research Project of Wenzhou(G20190006);Basic Scientific Research Project of Wenzhou(G20190003)

摘要/Abstract

摘要：

物理不可克隆函数（PUF，physically unclonable function）通过提取芯片制造过程中无法避免引入的工艺偏差，可产生具有随机性、唯一性和防篡改特性的特征密钥。通过对 PUF 电路结构和工作原理的研究，提出一种基于现场可编程门阵列（FPGA，field-programmable gate array）的新型强弱混合型 PUF （SWPUF，strong and weak PUF）电路设计方案。该PUF可根据激励的汉明重量(HW，hamming weight)灵活地配置为强PUF和弱PUF两种拓扑结构，解决强/弱PUF分立实现的局限性。此外，利用异或去相关技术进一步优化输出密钥的统计特性。所提PUF采用Xilinx Artix-7 FPGA（28 nm工艺）实现，利用Matlab结合MicroBlaze微控制器构建内建自测试平台（self-built test platform）。实验结果表明，该PUF具有良好的随机性（96.98%）、唯一性（99.64%）和可靠性（常温常压下96.6%）。逻辑回归分析进一步显示，在HW较小的情况下所提SWPUF比传统的Arbiter-PUF具有更好的抗攻击能力，可广泛应用于信息安全领域，如密钥存储（针对弱PUF）和设备认证（针对强PUF）。

关键词: 强弱混合型, 物理不可克隆函数, 现场可编程门阵列, 电路设计

Abstract:

Physically unclonable function (PUF) can produce intrinsic keys with characteristics of randomness, uniqueness and tamper-proof by exploiting the process deviations which can not be avoided in the chip manufacturing process.A novel hybrid strong and weak PUF (SWPUF) circuit design based on field-programmable gate array(FPGA) was proposed after the investigation of the PUF circuit structures and principles.To address the limitation of designing strong-PUF and weak-PUF discretely, SWPUF could be configured into two topologies conveniently depending on the Hamming Weight (HW) of the challenges.In addition, the statistical characteristics of the responses could be further improved by a XOR-decorrelation technique.The proposed SWPUF was implemented on a Xilinx Artix-7 FPGA (28nm technology), and a self-built test platform was set up by using Matlab and MicroBlaze microcontroller.Experimental results show that the SWPUF has good performances of randomness (96.98%), uniqueness (99.64%) and reliability (96.6%).Logic register analysis also shows that the SWPUF has a better anti-attack capability than the traditional Arbiter-PUF in the case of with small HW, and can be used in the information security, such as key storage (especially to weak PUF) and device authentication (especially to strong PUF).

Key words: hybrid strong and weak, physically unclonable function, FPGA, circuit design

中图分类号:

TP309

连佳娜, 汪鹏君, 李刚, 马雪娇, 翟官宝. 基于FPGA的新型强弱混合型PUF电路设计[J]. 网络与信息安全学报, 2021, 7(2): 94-103.

Jiana LIAN, Pengjun WANG, Gang LI, Xuejiao MA, Guanbao ZHAI. Novel hybrid strong and weak PUF design based on FPGA[J]. Chinese Journal of Network and Information Security, 2021, 7(2): 94-103.

图/表 16

图1

图2

表1

由N级开关单元组成的弱PUF的激励（HW=1） Table 1 Challenge of weak PUF composed of N switch units (HW=1)"

激励	C₀	C₁	C₂	C₃	…	C_n
激励1	1	0	0	0	…	0
激励2	0	1	0	0	…	0
激励3	0	0	1	0	…	0
激励4	0	0	0	1	…	0
$⋮$	$⋮$	$⋮$	$⋮$	$⋮$	…	$⋮$
激励N	0	0	0	0	…	1

表1

图3

图4

图5

表2

图6

表3

图7

图8

图9

图10

图11

图12

表4

参考文献 36

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时钟脉冲	输入序列值	状态S（初值为0101）				输出R
时钟脉冲	输入序列值	a₁	a₂	a₃	a₄	输出R
1	1	1	0	1	1	1
2	0	0	1	1	0	0
3	0	1	1	0	0	0
4	1	1	0	0	1	0
5	0	0	0	0	1	0
6	1	1	0	1	0	1
7	1	1	1	0	1	1
8	0	0	0	1	1	0

移位寄存器位数n	异或间隔位数
移位寄存器位数n	0	1	2	3
4	46.94%	41.53%	—	—
6	49.65%	47.25%	50.82%	—
8	51.84%	48.48%	38.62%	38.52%
10	49.97%	49.67%	38.64%	38.62%
12	50.14%	50.29%	49.65%	49.89%
14	49.06%	48.91%	38.55%	38.64%
16	50.16%	50.11%	48.81%	50.07%
18	51.92%	51.29%	50.64%	38.65%
20	50.74%	50.15%	38.74%	50.81%

对比文献	随机性	唯一性	可靠性	响应位数	实现方式	工艺/nm
Racing APUF^[30]	92.6%	—	91.6%	—	FPGA	65
multi-line APUF^[31]	99.4%	93%	99.9%	64	FPGA	65
APUF^[32]	90.4%	92.8%	99.3%	64	FPGA	65
DAPUF^[32]	91.4%	82.6%	90.2%	64	FPGA	65
XRBR PUF^[33]	—	81.34%	98.22%	—	FPGA	45
XRRO PUF^[33]	—	97.52%	97.72%	—	FPGA	45
RO PUF^[18]	84.58%	96.02%	98.25%	1024	FPGA	28
Zhang PUF^[34]	89.8%	99.2%	96.3%	64	FPGA	28
基于延迟的PUF^[35]	90.8%	99.4%	96.8%	64	FPGA	28
FF-APUF^[36]	80%	83.06%	97.1%	64	FPGA	28
本文所提SWPUF	96.98%	99.64%	96.6%	256	FPGA	28
注：“—”表示无法获得。

基于FPGA的新型强弱混合型PUF电路设计

Novel hybrid strong and weak PUF design based on FPGA

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