Chinese Journal of Network and Information Security ›› 2018, Vol. 4 ›› Issue (12): 16-24.doi: 10.11959/j.issn.2096-109x.2018100

• Papers • Previous Articles     Next Articles

Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis

Qinrang LIU,Chongyang LIU(),Jun ZHOU,Xiaolong WANG   

  1. National Digital Switching System Engineering and Technological R&D Center,Zhengzhou 450002,China
  • Revised:2018-10-29 Online:2018-12-01 Published:2018-12-30
  • Supported by:
    The National Science Technology Major Project of China(2016ZX01012101);The National Natural Science Foundation of China(61572520);The National Natural Science Foundation Innovation Group Project of China(61521003)


Concerning the issue that the convolutional neural network (CNN) accelerator design on most FPGA ends fails to effectively use the sparsity and considering both bandwidth and energy consumption,two improved CNN calculation optimization strategies based on linear systolic array architecture are proposed.Firstly,convolution is transformed into matrix multiplication to take advantage of sparsity.Secondly,in order to solve the problem of large I/O demand in traditional parallel matrix multiplier,linear systolic array is used to improve the design.Finally,a CNN acceleration comparative analysis of the advantages and disadvantages between parallel matrix multiplier and two improved linear systolic arrays is presented.Theoretical proof and analysis show that compared with the parallel matrix multiplier,the two improved linear systolic arrays make full use of sparsity,and have the advantages of less energy consumption and less I/O bandwidth occupation.

Key words: linear systolic array, convolutional neural network, sparsity, I/O bandwidth, performance analysis

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