[1] |
LE Q , YANG G , HUNG W N N , et al. Pareto optimal mapping for tile-based network-on-chip under reliability constraints[J]. Interna-tional Journal of Computer Mathematics, 2015,92(1):41-58.
|
[2] |
KUMAR S , JANTSCH A , SOININEN J P , et al. A network on chip architecture and design methodology[C]// VLSI, 2002. IEEE Computer Society Annual Symposium. IEEE, Pittsburgh, Pennsylvania, 2012:105-112.
|
[3] |
SAHU P K , CHATTOPADHYAY S . A survey on application mapping strategies for network-on-chip design[J]. Journal of Systems Architec-ture, 2013,59(1):60-76.
|
[4] |
BJERREGAARD T , MAHADEVAN S . A survey of research and practices of network-on-chip[J]. ACM Computing Surveys (CSUR), 2006,38(1):1.
|
[5] |
ELMILIGI H , EL-KHARASHI M W , GEBALI F . Power consumption of 3D networks-on-chips: modeling and optimization[J]. Microproc-essors and Microsystems, 2013,37(6):530-543.
|
[6] |
CHENG Y , ZHANG L , HAN Y , et al. Thermal-constrained task allo-cation for interconnect energy reduction in 3D homogeneous mpsocs[J]. Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 2013,21(2):239-249.
|
[7] |
TOSUN S , OZTURK O , OZEN M . An ILP formulation for application mapping onto Network-on-Chips[C]// Application of Information and Communication Technologies, 2009. AICT 2009. International Con-ference IEEE, Baku, Azerbaijan. 2009:1-5.
|
[8] |
PLANIVELOO V A , AMBROSE J A , SOWMYA A , et al. Improving GA-based NoC mapping algorithms using a formal model[C]// VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium. IEEE, Florida, USA, 2014:344-349.
|
[9] |
王佳文, 李丽, 易伟 , 等. 3D NoC 映射问题的动态蚁群算法[J]. 计算机辅助设计与图形学学报, 2011,23(9):1614-1620. WANG J W , LI L , YI W , et al. A dynamic ant colony optimization al-gorithm for 3D NoC mapping[J]. Journal of Computer-Aided Design& Computer Graphics. 2011,23(9):1614-1620.
|
[10] |
杨盛光, 李丽, 高明伦 , 等. 面向能耗和延时的 NoC 映射方法[J]. 电子学报, 2008,36(5):937-942. YANG S G , LI L , GAO M L , et al. An energy-and delay-aware map-ping method of NoC[J]. Acta Electronic Sinica, 2008,36(5):937-942.
|
[11] |
RAHMANI A M , LILJEBERG P , PLOSILA J , et al. Developing a power-efficient and low-cost 3D NoC using smart GALS-based verti-cal channels[J]. Journal of Computer and System Sciences, 2013,79(4):440-456.
|
[12] |
ZHANG T , WU N , ZHOU F , et al. A traffic equilibrium mapping method with energy minimization for 3D NoC-Bus mesh architec-ture[J]. IAENG International Journal of Computer Science, 2015,42(1):1-7.
|
[13] |
WANG X , PALESI M , YANG M , et al. Power-aware run-time incre-mental mapping for 3-D networks-on-chip[C]// Network and Parallel Computing. Springer Berlin Heidelberg, 2011:232-247.
|
[14] |
李东生, 刘琪 . 面向通信能耗的3D NoC映射研究[J]. 半导体技术, 2012,37(7):504-507. LI D S , LIU Q . Research on mapping 3D network on chip for commu-nication energy-aware[J]. Semiconductor Technology, 2012,37(7):504-507.
|
[15] |
史峰, 王辉, 郁磊 , 等. Matlab 智能算法30个案例分析[M]. 北京航空航天大学出版社, 2011. SHI F , WANG H , YU L , et al. Matlab intelligent algorithm analusis of 30 cases[M]. Beihang University Press, 2011.
|
[16] |
SAHU P K , SHAH T , MANNA K , et al. Application mapping onto mesh-based network-on-chip using discrete particle swarm optimiza-tion[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014,22(2):300-312.
|
[17] |
DICK R P , RHODES D L , WOLF W . TGFF: task graphs for free[C]// The 6th International Workshop on Hardware/Software codesign. IEEE Computer Society. 1998:97-101.
|
[18] |
Available online[EB/OL]. , 2015.4.29.
|