通信学报 ›› 2012, Vol. 33 ›› Issue (11): 165-170.doi: 10.3969/j.issn.1000-436x.2012.11.021

• 学术通信 • 上一篇    下一篇

基于FPGA的部分并行QC-LDPC译码器高效存储方法

袁瑞佳1,2,白宝明1,2   

  1. 1 西安电子科技大学 综合业务网国家重点实验室,陕西 西安 710071
    2 中电科技集团公司第54研究所 通信网信息传输与分发技术重点实验室,河北 石家庄 050002
  • 出版日期:2012-11-25 发布日期:2017-07-25
  • 基金资助:
    国家重点基础研究发展计划(“973”计划)基金资助项目;国家自然科学基金资助项目;国家科技重大专项基金资助项目;通信网信息传输与分发技术重点实验室开放课题基金资助项目

Efficient storage method for FPGA-based partially parallel QC-LDPC decoder

Rui-jia YUAN1,2,Bao-ming BAI1,2   

  1. 1 State Key Lab of Integrated Services Networks,Xidian University,Xi’an 710071,China
    2 Science and Technology on Information Transmission and Dissemination in Communication Networks Lab,CETC No.54 Research Institute,Shijiazhuang 050002,China
  • Online:2012-11-25 Published:2017-07-25
  • Supported by:
    The National Basic Research Program of China (973 Program);The National Natural Science Foundation of China;The National S&T Major Project of China;Science and Technology on Information Transmission and Dissemination in Communication Networks Laboratory

摘要:

针对部分并行结构的准循环低密度校验(QC-LDPC)码译码器,提出了一种将译码准码字存储在信道信息和外信息存储块中的高效存储方法,该方法不需要额外的存储块来存储译码准码字,能够减少译码器实验所需的存储资源数量,并且有效降低了译码电路的布线复杂度。在Xilinx XC2V6 000-5ff1 152 FPGA上的实验结果表明,提出的QC-LDPC码译码器设计方法能够在降低系统的BRAM资源需求量的同时有效地提高系统的运行频率和译码吞吐量。

关键词: LDPC码, 译码器, 部分并行, 高效存储, FPGA实验

Abstract:

An efficient storage method of hard decisions sharing intrinsic and extrinsic memory banks for partially parallel QC-LDPC decoder was proposed.Extra memory banks for storing hard decisions were avoided in this method,which result in significantly reduced consumption of RAM resources and routed complexity.Implementation results based on a Xilinx XC2V6 000-5ff1 152 FPGA show that the proposed method improves the frequency and decodes throughput of the system,and significantly reduced the requirements for the number of BRAM.

Key words: LDPC code, decoder, partially parallel, efficient storage, FPGA implementation

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