一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

doi:10.11959/j.issn.1000-0801.2022023

电信科学 ›› 2022, Vol. 38 ›› Issue (2): 47-58.doi: 10.11959/j.issn.1000-0801.2022023

一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

张茜⁴⁷, 詹明⁴⁸, 章坚武⁴⁹, 王富龙¹, 冯云开¹, 唐浩¹

¹ 西南大学，重庆 400715
² 杭州电子科技大学，浙江杭州 310018

修回日期:2022-01-28 出版日期:2022-02-20 发布日期:2022-02-01
作者简介:张茜（1996- ），女，西南大学硕士生，主要研究方向为信号与信息处理
詹明（1975- ），男，博士，西南大学学院教授、博士生导师，中国电子学会会员，主要研究方向为信道编码理论与技术、无线传感器网络、超高性能工业无线控制
章坚武（1961- ），男，博士，杭州电子科技大学教授、博士生导师，中国电子学会高级会员，浙江省通信学会常务理事，主要研究方向为移动通信、多媒体信号处理与人工智能、通信网络与信息安全
王富龙（1995- ），男，西南大学硕士生，主要研究方向为信号与信息处理
冯云开（1995- ），男，西南大学硕士生，主要研究方向为信号与信息处理
唐浩（1996- ），男，西南大学硕士生，主要研究方向为信号与信息处理
基金资助:
国家自然科学基金资助项目(61671390)

Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

Qian ZHANG⁴⁷, Ming ZHAN⁴⁸, Jianwu ZHANG⁴⁹, Fulong WANG¹, Yunkai1 FENG¹, Hao TANG¹

¹ Southwest University, Chongqing 400715, China
² Hangzhou Dianzi University, Hangzhou 310018, China

Revised:2022-01-28 Online:2022-02-20 Published:2022-02-01
Supported by:
The National Natural Science Foundation of China(61671390)

摘要/Abstract

摘要：

为满足无线通信中高吞吐、低功耗的要求，并行译码器的结构设计得到了广泛的关注。基于并行Turbo码译码算法，研究了前后向度量计算中的对称性，提出了一种基于前后向合并计算的高效并行 Turbo 码译码器结构设计方案，并进行现场可编程门阵列（field-programmable gate array，FPGA）实现。结果表明，与已有的并行 Turbo 码译码器结构相比，本文提出的设计结构使状态度量计算模块的逻辑资源降低 50%左右，动态功耗在125 MHz频率下降低5.26%，同时译码性能与并行算法的译码性能接近。

关键词: 状态度量合并计算, Turbo码, FPGA实现, 并行算法

Abstract:

In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed, and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that, compared with the existing parallel Turbo decoder architectures, the proposed design architecture reduces the logic resource of state metrics calculation module about 50%, while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.

Key words: state measure merge calculation, Turbo code, FPGA implementation, parallel algorithm

中图分类号:

TN929

张茜, 詹明, 章坚武, 王富龙, 冯云开, 唐浩. 一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现[J]. 电信科学, 2022, 38(2): 47-58.

Qian ZHANG, Ming ZHAN, Jianwu ZHANG, Fulong WANG, Yunkai1 FENG, Hao TANG. Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations[J]. Telecommunications Science, 2022, 38(2): 47-58.

图/表 14

图1

图2

图3

图4

图5

图6

图7

图8

表1

度量值量化方案"

度量值类型	$y_{k}^{s}, y_{k}^{p_{1}}, y_{k}^{p_{2}}$	${\tilde{α}}_{k}, {\tilde{β}}_{k}, {\tilde{γ}}_{k}^{}$	$Λ_{apo, k}$
(q,f)	(5,3)	(10,3)	(11,3)

表1

表2

图9

图10

图11

图12

参考文献 22

[1]	田甜, 薛鸿民, 邓志龙 . Turbo码在短波通信系统中的应用研究[J]. 科技资讯, 2020,18(24): 49-51,63.
	TIAN T , XUE H M , DENG Z L . Application research of turbo code in short wave communication system[J]. Science ＆ Technology Information, 2020,18(24): 49-51,63.
[2]	郭臣, 付高原, 杨茂辉 . 基于FPGA的Turbo码数据传输系统的实现[J]. 电子测量技术, 2017,40(10): 221-225.
	GUO C , FU G Y , YANG M H . Implementation of Turbo codes data transmission system on the basis of FPGA[J]. Electronic Measurement Technology, 2017,40(10): 221-225.
[3]	FIGUEIREDO F A P , MATHILDE F , CARRILLO D ,et al. A framework for the automation of LTE physical layer tests[J]. Wireless Personal Communications, 2018,102(1): 293-307.
[4]	陈发堂, 刘一帆, 唐成 . 一种用于5G IOT通信的能量效率方案[J]. 电子技术应用, 2017,43(11): 2-6,26.
	CHEN F T , LIU Y F , TANG C . An energy-efficient scheme for 5G Internet of Things[J]. Application of Electronic Technique, 2017,43(11): 2-6,26.
[5]	3GPP. Multiplexing and channel coding (Release 11):TS 36.212 v11.3.0[S]. 2013.
[6]	詹明, 文红, 伍军 . LTE-Advanced标准中一种基于反向重算的低存储容量Turbo码译码器结构设计[J]. 电子学报, 2017,45(7): 1584-1592.
	ZHAN M , WEN H , WU J . A memory reduced turbo code decoding architecture for LTE-Advanced standard based on reverse recalculation[J]. Acta Electronica Sinica, 2017,45(7): 1584-1592.
[7]	LI Y , XU B J , MA L ,et al. High-throughput error correction for continuous-variable quantum key distribution systems based on shuffled iterative decoding[C]// Proceedings of SPIE/COS Photonics Asia.Proc SPIE 11558,Quantum and Nonlinear Optics VII,Online Only.[S.l.:s.n.], 2020,11558: 77-82.
[8]	YOO I , KIM B , PARK I C . Tail-overlapped SISO decoding for high-throughput LTE-advanced turbo decoders[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2014,61(9): 2711-2720.
[9]	LIN J S , SHIEH M D , LIU C Y ,et al. Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced[J]. VLSI Design,Automation and Test (VLSI-DAT), 2015: 1-4.
[10]	PARVATHY M , GANESAN R . Throughput enhancement of SISO parallel LTE turbo decoders using floating point turbo decoding algorithm[J]. International Journal of Wireless and Mobile Computing, 2018,15(1): 58.
[11]	GONZALEZ-PEREZ L F , YLLESCAS-CALDERON L C , PARRA-MICHEL R , . Parallel and configurable turbo decoder implementation for 3GPP-LTE[C]// Proceedings of 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig). Piscataway:IEEE Press, 2013: 1-6.
[12]	MAUNDER R G . A fully-parallel turbo decoding algorithm[J]. IEEE Transactions on Communications, 2015,63(8): 2762-2775.
[13]	LI A , XIANG L P , CHEN T H ,et al. VLSI implementation of fully parallel LTE turbo decoders[J]. IEEE Access, 2016,4: 323-346.
[14]	LI A , HAILES P , MAUNDER R G ,et al. 1.5 Gbit/s FPGA implementation of a fully-parallel turbo decoder designed for mission-critical machine-type communication applications[J]. IEEE Access, 2016(4): 5452-5473.
[15]	TRAN M T , GAUTIER M , CASSEAU E . On the FPGA-based implementation of a flexible waveform from a high-level description:application to LTE FFT case study[C]// Proceedings of Cognitive Radio Oriented Wireless Networks.[S.l.:s.n.], 2016.
[16]	MURUGAPPA P , BAZIN J N , BAGHDADI A ,et al. FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding[C]// Proceedings of 2012 23rd IEEE International Symposium on Rapid System Prototyping. Piscataway:IEEE Press, 2012: 143-148.
[17]	孙增友, 李欢欢, 王蒙 ,等. 采用近似max*运算的Log-MAP译码算法[J]. 计算机应用与软件, 2016,33(3): 255-258.
	SUN Z Y , LI H H , WANG M ,et al. Log-map decoding algorithm using approximate max*operation[J]. Computer Applications and Software, 2016,33(3): 255-258.
[18]	付婉, 杨茂辉, 胡明亮 ,等. Turbo 码译码算法理论推导及误码性能分析[J]. 电子测量技术, 2018,41(11): 10-14.
	FU W , YANG M H , HU M L ,et al. Theoretical derivation and error performance analysis of Turbo decoding algorithm[J]. Electronic Measurement Technology, 2018,41(11): 10-14.
[19]	SYBIS M , . Chebyshev inequality based max* approximation for reduced complexity decoding of turbo TCM[C]// Proceedings of 2010 6th International Symposium on Turbo Codes ＆ Iterative Information Processing. Piscataway:IEEE Press, 2010: 265-269.
[20]	MISHRA S , SHUKLA H , MADHEKAR S . Implementation of Turbo decoder using MAX-LOGMAP algorithm in VHDL[C]// Proceedings of 2015 Annual IEEE India Conference. Piscataway:IEEE Press, 2015: 1-6.
[21]	GAO Z , ZHANG L L , YAN T ,et al. Design of SEU-tolerant turbo decoders implemented on SRAM-FPGAs[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020,28(12): 2563-2572.
[22]	ZHAN M , PANG Z B , YU K ,et al. Reverse calculation-based low memory turbo decoder for power constrained applications[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2021,68(6): 2688-2701.

设计方案	逻辑单元/个	寄存器/个	寄存器容量/bit
并行设计方案	3 044	572	10 240
本文设计的方案	1 583	396	10 060

一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

在线阅读

PDF下载

可视化

摘要/Abstract

引用本文

使用本文

图/表 14

参考文献 22

相关文章 3

Metrics

推荐阅读 0

[1]	王艳君,岳婧,崔雪. 窄带通信系统中信道编码系统的改进[J]. 电信科学, 2013, 29(5): 113-117.
[2]	郭健,苏军峰,谈振辉. LTE系统中Turbo译码的改进算法[J]. 电信科学, 2011, 27(6): 74-78.
[3]	袁伟,马卓,何勃,赵彦. 一种适用于COFDM系统的低复杂度噪声功率估计算法[J]. 电信科学, 2010, 26(8): 114-118.