Abstract: This paper presents a high-throughput, hybrid word-length, mixed-radix, four-parallel data-path 128-point FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed processor uses an error compensation method for modified booth fixed-width multipliers and canonic signed digit (CSD) multipliers, which leads to higher precision and lower hardware complexity. From analysis, it is shown that the proposed architecture can save 49% multipliers utilizations compared to MRMDF architecture, additional our proposed architecture can save 30% memory resource and be increased by 33% throughput rate compared to the two- parallel data-path architecture under the same hardware cost. So it makes the best balance of the precision, the hardware cost and the speed. Also, ours processor is designed using 0.18 μm COMS process with a throughput rate of up to 1.2 Gsample/s at 300 MHz, which meets the requirements for gigabit WPAN.