[1] |
DANG V , FARAHMAND F , ANDRZEJCZAK M ,et al. Implementation and benchmarking of round 2 candidates in the NIST post-quantum cryptography standardization process using hardware and software/hardware co-design approaches[J]. IACR Cryptol EPrint Arch,2020, 2020:795.
|
[2] |
AVANZI R , BOS J , DUCAS L ,et al. CRYSTALS-Kyber[R]. 2017.
|
[3] |
LYUBASHEVSKY V , SEILER G . NTTRU:truly fast NTRU using NTT[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019,2019(3): 180-201.
|
[4] |
ZHANG N , QIN Q , YUAN H ,et al. NTTU:an area-efficient low-power NTT-uncoupled architecture for NTT-based multiplication[J]. IEEE Transactions on Computers, 2020,69(4): 520-533.
|
[5] |
YAMAN F , MERT A C , ?ZTüRK E ,et al. A hardware accelerator for polynomial multiplication operation of CRYSTALS-Kyber PQC scheme[C]// Proceedings of 2021 Design,Automation & Test in Europe Conference & Exhibition (DATE). Piscataway:IEEE Press, 2021: 1020-1025.
|
[6] |
HUANG Y M , HUANG M Q , LEI Z K ,et al. A pure hardware implementation of CRYSTALS-KYBER PQC algorithm through resource reuse[J]. IEICE Electronics Express, 2020,17(17): 1-6.
|
[7] |
MERT A C , KARABULUT E , OZTURK E ,et al. An extensive study of flexible design methods for the number theoretic transform[J]. IEEE Transactions on Computers, 2020:doi.org/10.1109/TC.2020.3017930.
|
[8] |
MERT A C , ?ZTüRK E , SAVA? E . Design and implementation of a fast and scalable NTT-based polynomial multiplier architecture[C]// Proceedings of 2019 22nd Euromicro Conference on Digital System Design (DSD). Piscataway:IEEE Press, 2019: 253-260.
|
[9] |
XING Y F , LI S G . A compact hardware implementation of CCA-secure key exchange mechanism CRYSTALS-Kyber on FPGA[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2021,2021(2): 328-356.
|
[10] |
RICCI S , JEDLICKA P , CIBIK P ,et al. Towards CRYSTALS-Kyber VHDL implementation[C]// Proceedings of the 18th International Conference on Security and Cryptography.[S.l. ]:Science and Technology Publications, 2021: 760-765.
|
[11] |
RICCI S , MALINA L , JEDLICKA P ,et al. Implementing CRYSTALS-dilithium signature scheme on FPGAs[C]// Proceedings of 16th International Conference on Availability,Reliability and Security. New York:ACM Press, 2021: 1-11.
|
[12] |
CHEN Z H , MA Y , CHEN T Y ,et al. Towards efficient kyber on FPGAs:a processor for vector of polynomials[C]// Proceedings of 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). Piscataway:IEEE Press, 2020: 247-252.
|
[13] |
SEILER G . Faster AVX2 optimized NTT multiplication for ring-LWE lattice cryptography[J]. IACR Cryptology EPrint Archive,2018, 2018:39.
|
[14] |
ZIJLSTRA T , BIGOU K , TISSERAND A . Lattice-based cryptosystems on FPGA:parallelization and comparison using HLS[J]. IEEE Transactions on Computers, 2021:doi.org/10.1109/TC.2021.3112052.
|
[15] |
BASU K , SONI D , NABEEL M ,et al. NIST post-quantum cryptography-a hardware evaluation study[R]. 2019.
|
[16] |
AGRAWAL R , BU L K , EHRET A ,et al. Open-source FPGA implementation of post-quantum cryptographic hardware primitives[C]// Proceedings of 2019 29th International Conference on Field Programmable Logic and Applications (FPL). Piscataway:IEEE Press, 2019: 211-217.
|
[17] |
BISHEH-NIASAR M , AZARDERAKHSH R , MOZAFFARI-KERMANI M . High-speed NTT-based polynomial multiplication accelerator for post-quantum cryptography[C]// Proceedings of 2021 IEEE 28th Symposium on Computer Arithmetic (ARITH). Piscataway:IEEE Press, 2021: 94-101.
|
[18] |
FRITZMANN T , SIGL G , SEPúLVEDA J . RISQ-V:tightly coupled RISC-V accelerators for post-quantum cryptography[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020: 239-280.
|
[19] |
陈朝晖, 马原, 荆继武 . 格密码关键运算模块的硬件实现优化与评估[J]. 北京大学学报(自然科学版), 2021,57(4): 595-604.
|
|
CHEN Z H , MA Y , JING J W . Hardware optimization and evaluation for crucial modules of lattice-based cryptography[J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2021,57(4): 595-604.
|
[20] |
刘冬生, 赵文定, 刘子龙 ,等. 应用于格密码的可重构多通道数论变换硬件设计[J]. 电子与信息学报, 2021:doi.org/10.11999/ JEIT210114.
|
|
LIU D S , ZHAO W D , LIU Z L ,et al. Reconfigurable hardware design of multi-lanes number theoretic transform for lattice-based cryptography[J]. Journal of Electronics & Information Technology, 2021:doi.org/10.11999/ JEIT210114.
|
[21] |
华斯亮, 张惠国, 王书昶 . 用于全同态加密的数论变换乘法蝶形运算优化及实现[J]. 电子与信息学报, 2021,43(5): 1381-1388.
|
|
HUA S L , ZHANG H G , WANG S C . Optimization and implementation of number theoretical transform multiplier butterfly operation for fully homomorphic encryption[J]. Journal of Electronics & Information Technology, 2021,43(5): 1381-1388.
|
[22] |
沈诗羽, 何峰, 赵运磊 . Aigis密钥封装算法多平台高效实现与优化[J]. 计算机研究与发展, 2021,58(10): 2238-2252.
|
|
SHEN S Y , HE F , ZHAO Y L . Multi-platform efficient implementation and optimization of aigis-enc algorithm[J]. Journal of Computer Research and Development, 2021,58(10): 2238-2252.
|
[23] |
ZHANG N , YANG B H , CHEN C ,et al. Highly efficient architecture of NewHope-NIST on FPGA using low-complexity NTT/INTT[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020,2020(2): 49-72.
|