开源芯片、RISC-V与敏捷开发

doi:10.11959/j.issn.2096-0271.2019032

大数据 ›› 2019, Vol. 5 ›› Issue (4): 50-66.doi: 10.11959/j.issn.2096-0271.2019032

• 专题：大数据的系统结构 • 上一篇下一篇

开源芯片、RISC-V与敏捷开发

王诲喆^1,²,唐丹¹,余子濠^1,²,刘志刚¹,解壁伟¹,包云岗^1,²

¹ 中国科学院计算技术研究所计算机体系结构国家重点实验室，北京 100190
² 中国科学院大学，北京 100049

出版日期:2019-07-15 发布日期:2019-08-09
作者简介:王诲喆（1994- ），男，中国科学院计算技术研究所计算机体系结构国家重点实验室先进计算机系统研究中心硕士生。目前负责标签化体系结构的研发及其在RISC-V平台的应用，主要研究方向为计算机系统的性能优化与实现。|唐丹（1976- ），男，博士，中国科学院计算技术研究所高级工程师，中国计算机学会（CCF）会员，主要研究方向为计算机体系结构，长期从事高性能处理器I/O系统及超低功耗SoC芯片的研究与开发工作。在HPCA和JCST等高水平会议和期刊上发表多篇论文，获得多项国家发明专利。|余子濠（1991- ），男，中国科学院计算技术研究所计算机体系结构国家重点实验室先进计算机系统研究中心博士生，主要研究方向为计算机体系结构。|刘志刚（1995- ），男，中国科学院计算技术研究所计算机体系结构国家重点实验室先进计算机系统研究中心硕士生，研究方向为计算机体系结构。|解壁伟（1987- ），男，博士，中国科学院计算技术研究所助理研究员，主要研究方向为计算机体系结构、EDA技术和高性能计算等。|包云岗（1980- ），男，博士，中国科学院计算技术研究所研究员，计算机体系结构国家重点实验室教授，先进计算机系统研究中心主任，中国科学院大学岗位教授。担任中国计算机学会理事、普及工作委员会主任，中国科学院青年创新促进会理事。主要研究方向为计算机系统结构，主持研制多款达到国际先进水平的系统，在国际会议期刊发表了40余篇论文，相关技术在华为技术有限公司、阿里巴巴集团、英特尔公司等国内外企业应用，多次受邀担任ASPLOS、ISCA、MICRO、SC等国际会议的程序委员会委员。
基金资助:
国家重点研发计划基金资助项目(2016YFB100020);国家自然科学基金资助项目(61420106013);中国科学院青年创新促进会优秀会员基金资助项目(2013073)

Open-source chip,RISC-V and agile development

Huizhe WANG^1,²,Dan TANG¹,Zihao YU^1,²,Zhigang LIU¹,Biwei XIE¹,Yungang BAO^1,²

¹ Key Laboratory of Computer System and Architecture,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China
² University of Chinese Academy of Sciences,Beijing 100049,China

Online:2019-07-15 Published:2019-08-09
Supported by:
National Key Research and Development Program of China(2016YFB100020);The National Natural Science Foundation of China(61420106013);Youth Innovation Promotion Association of Chinese Academy of Sciences(2013073)

摘要/Abstract

摘要：

随着摩尔定理的几近失效，传统的追求通用性能的芯片开发策略将难以持续，但芯片领域过高的门槛和商业限制阻碍了进一步的创新和对市场的响应速度。因此需要通过开源芯片、统一的生态平台和现代化的设计方法激发芯片领域的创造力和生产效率。介绍了开源芯片的作用和发展历史，讨论了有望成为下一代芯片开发根基的RISC-V指令集架构的特点和影响以及前端设计中的敏捷开发实践，并对芯片开发的新发展与不足做出了总结。

关键词: 开源芯片, 敏捷开发, 计算机架构, 指令集架构

Abstract:

Due to the end of Moore’s Law,traditional chip developing effort focusing on general-purpose performance cannot last long.However,the high entrance requirements and commercial limits block the further innovation and delay its time to market.Therefore open-source chips,universal platform and modern developing methodology are essential.The significance and development of open-source chips,the merit and impact of RISC-V instruction architecture and the agile development practice in logical design were introduced,and this new trend and its remaining defects were commented on in the end.

Key words: open-source chip, agile development, computer architecture, instruction set architecture

中图分类号:

TP303

王诲喆,唐丹,余子濠,刘志刚,解壁伟,包云岗. 开源芯片、RISC-V与敏捷开发[J]. 大数据, 2019, 5(4): 50-66.

Huizhe WANG,Dan TANG,Zihao YU,Zhigang LIU,Biwei XIE,Yungang BAO. Open-source chip,RISC-V and agile development[J]. Big Data Research, 2019, 5(4): 50-66.

图/表 5

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特性	Chisel	SystemVerilog	Verilog
信号整体连接	支持	支持，但有局限性	不支持
元编程	支持	部分支持且不可综合	不支持
面向对象编程	支持	部分支持且不可综合	不支持
函数式编程	支持	不支持	不支持

开源芯片、RISC-V与敏捷开发

Open-source chip,RISC-V and agile development

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