通信学报 ›› 2023, Vol. 44 ›› Issue (4): 15-26.doi: 10.11959/j.issn.1000-436x.2023046

• 学术论文 • 上一篇    下一篇

联合重采样的并行双反馈时频域符号定时恢复算法

张沛鑫1, 张南1, 王大庆2, 吴桐2, 李哲1, 宫丰奎1   

  1. 1 西安电子科技大学空天地一体化综合业务网全国重点实验室,陕西 西安 710071
    2 西安空间无线电技术研究所,陕西 西安 710100
  • 修回日期:2023-01-04 出版日期:2023-04-25 发布日期:2023-04-01
  • 作者简介:张沛鑫(1998- ),男,陕西汉中人,西安电子科技大学博士生,主要研究方向为高通量卫星通信系统、物理层可靠通信
    张南(1980- ),女,湖北天门人,博士,西安电子科技大学讲师、硕士生导师,主要研究方向为复杂环境下的通信系统关键技术
    王大庆(1980- ),男,山东枣庄人,西安空间无线电技术研究所研究员,主要研究方向为卫星通信
    吴桐(1990- ),男,陕西渭南人,博士,西安空间无线电技术研究所高级工程师,主要研究方向为卫星通信
    李哲(1996- ),男,陕西铜川人,西安电子科技大学硕士生,主要研究方向为单载波定时同步技术
    宫丰奎(1979- ),男,山东潍坊人,博士,西安电子科技大学教授、博士生导师,主要研究方向为宽带卫星互联网、自动化卫星地面检测设备研制、先进数字视频传输等
  • 基金资助:
    国家自然科学基金资助项目(62001354)

Joint resampling algorithm for parallel dual feedback time-frequency domain symbol timing recovery

Peixin ZHANG1, Nan ZHANG1, Daqing WANG2, Tong WU2, Zhe LI1, Fengkui GONG1   

  1. 1 State Key Laboratory of Integrated Service Networks, Xidian University, Xi’an 710071, China
    2 CAST-Xi’an Institute of Space Radio Technology, Xi’an 710100, China
  • Revised:2023-01-04 Online:2023-04-25 Published:2023-04-01
  • Supported by:
    The National Natural Science Foundation of China(62001354)

摘要:

针对现有符号定时恢复实现算法难以兼顾大吞吐量、高收敛精度和强抗定时误差算法能力的问题,提出一种联合重采样的高速并行定时恢复算法,利用双反馈环实现定时频偏和定时相偏的纠正。在设计并行重采样时,提出并行数控振荡器的实现方式以及利用使能排序和移位寄存器的方式来实现数据重排序。在进行定时恢复环路设计时,分析并推导O&M定时误差估计算法的并行实现结构,在对定时相/频偏纠正原理分析的基础上提出环路纠正的设计方法和实现结构。FPGA实测结果表明,所提算法能够实现最高64APSK调制信号4~16倍任意倍符号率的符号定时恢复,且与理想信号的误差向量幅度(EVM)在4%以内,满足宽带卫星通信需求。

关键词: 宽带卫星通信, 符号定时恢复, 双反馈, 并行实现

Abstract:

Aiming at the problem that it is difficult for existing implementation algorithms of symbol timing recovery to give full consideration to high convergence accuracy and the robustness to resist timing deviation, a high-speed parallel symbol timing recovery algorithm with resampling was proposed.The timing frequency offset and timing phase offset were corrected by using double feedback loops.In the design of parallel resampling, the implementation of parallel numerically controlled oscillators and the use of enable signals sorting and shift registers to implement data reordering were proposed.When designing the timing recovery loop, the parallel implementation structure of the O&M timing error estimation algorithm was analyzed and deduced, and the design method and implementation structure of the loop correction were proposed based on the analysis of the timing phase/frequency offset correction principle.The FPGA test results show that the proposed algorithm can realize the symbol timing recovery of 64APSK modulated signals with arbitrary multiple symbol rate between 4 and 16 times, and the error vector magnitude (EVM) with the ideal signal is within 4%, which meets the requirements of broadband satellite communication.

Key words: broadband satellite communication, STR, dual feedback, parallel implementation

中图分类号: 

No Suggested Reading articles found!