宽带数字阵列雷达通道固定时延误差估计技术的研究

doi:10.11959/j.issn.1000-436x.2023067

摘要/Abstract

摘要：

为解决宽带数字阵列雷达通道固定时延误差导致的数字波束成形性能下降问题，提出一种基于最大似然估计和抛物线插值的通道固定时延误差估计方法。该方法首先通过基带发射信号和包含未知时延参量的基带接收信号的相关积分后信号的峰值点估计通道固定时延整数部分；然后利用峰值点及其相邻两点进行抛物线插值完成通道固定时延小数部分估计；最后计算多通道固定时延误差，并完成各通道固定时延误差的补偿。仿真结果表明，该方法能够在赛灵思的xcku115平台下，实现宽带数字阵列雷达的多通道固定时延误差估计，并且在输入信号信噪比为10～30 dB的情况下，估计精度能够达到0.001～0.014倍采样间隔，可以满足工程的实际应用要求，提高宽带数字阵列雷达中数字波束成形的性能。

关键词: 数字阵列雷达, 通道时延估计, 最大似然估计, 抛物线插值

Abstract:

A channel-fixed delay error estimation method was proposed to tackle the performance degradation of digital beamforming caused by the channel-fixed delay error of wideband digital array radar.First, the integer part of the fixed delay of the channel was estimated through the correlation integral peak of the baseband transmitted signal and the baseband received signal containing unknown delay parameters.Then, the fractional part of the fixed delay of the channel was estimated with parabolic interpolation by using the correlation peak and its adjacent two points.Finally, the multi-channel fixed delay error was calculated and compensated.The simulation results show that the multi-channel fixed delay estimation of wideband digital array radar can be realized on Xilinx xcku115.The estimative precision can reach 0.001～0.014 times the sampling gap when the signal-to-noise ratio of the input signal is 10～30 dB.The proposed method can meet the engineering application requirements and improve the performance of digital beamforming in wideband digital array radar.

Key words: digital array radar, channel delay estimation, maximum likelihood estimation, parabolic interpolation

中图分类号:

TN967.51

张小贝, 张权, 方明, 秦琨, 张琦. 宽带数字阵列雷达通道固定时延误差估计技术的研究[J]. 通信学报, 2023, 44(3): 24-32.

Xiaobei ZHANG, Quan ZHANG, Ming FANG, Kun QIN, Qi ZHANG. Research on channel-fixed delay error estimation of wideband digital array radar[J]. Journal on Communications, 2023, 44(3): 24-32.

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参数类型	参数值
相对带宽	20％
阵元数量/个	8
阵元间距/m	0.015
波长/m	0.027 3
脉冲宽度/μs	1
主瓣方向	30°
目标距离/m	1 000

方法	波束指向	归一化主瓣增益/dB	归一化峰值副瓣电平/dB	归一化平均副瓣电平/dB
无通道固定时延误差	30°	0	–24.847	–22.885
通道固定时延误差标准差为20 ps	30.6°	–1.060	–14.498	–16.448
通道固定时延误差补偿后	30°	0.047	–24.160	–22.369

名称	方向	位宽/bit	功能
clk_300M	input	1	时钟信号
r_en	input	1	使能信号
rst_n	input	1	全局复位
ad_vaild	output	1	输出数据有效信号
ad1i_d0～ad1i_d3	output	14	通道0的I路输出
ad0q_d0～ad0q_d3	output	14	通道0的Q路输出

通道号	MATLAB仿真的多通道时延误差/采样间隔	FPGA多通道固定时延误差/采样间隔	误差/采样间隔
0	0	0	0
1	–0.028 581 6	–0.028 686 5	0.000 104 9
2	–0.009 652 3	–0.009 765 6	0.000 113 3
3	–0.030 333 7	–0.030 395 5	0.000 061 8
4	0.015 641 8	0.015 564 0	0.000 077 8
5	0.010 443 1	0.010 376 0	0.000 067 2
6	–0.016 455 6	–0.016 540 5	0.000 084 8
7	–0.036 536 8	–0.036 743 2	0.000 206 4