降低系统芯片中跨时钟域设计和验证复杂度的方法

doi:10.3969/j.issn.1000-436x.2012.11.019

通信学报 ›› 2012, Vol. 33 ›› Issue (11): 151-158.doi: 10.3969/j.issn.1000-436x.2012.11.019

降低系统芯片中跨时钟域设计和验证复杂度的方法

刘丹¹,冯毅²,党向磊²,佟冬²,程旭²,王克义²

¹ 北京大学深圳研究生院，广东深圳 518055
² 北京大学微处理器研发中心，北京 100871

出版日期:2012-11-25 发布日期:2017-07-25
基金资助:
国家高技术研究发展计划（“863”计划）基金资助项目

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

Dan LIU¹,Yi FENG²,Xiang-lei DANG²,Dong TONG²,Xu CHENG²,Ke-yi WANG²

¹ ShenZhen Graduate School,Peking University,Shenzhen 518055,China
² Microprocessor Research ＆ Development Center,Pekin niversity,Beijing 100871,China

Online:2012-11-25 Published:2017-07-25
Supported by:
The National High Technology Research and Development Program of China(863 Program)

摘要/Abstract

摘要：

在系统芯片设计中，直接采用现有的跨时钟域信号处理方法不仅设计复杂度高而且验证难度大。为了解决这个问题，将跨时钟域设计与功能设计完全分离，在每个通信接口部件中采用独立的、专用的跨时钟域处理模块统一解决跨时钟域信号的传输问题，并通过封装点对点通信接口和合并处理同一方向的跨时钟域信号，将需要处理的跨时钟域信号的数量减少为方向相反的2组。实验结果表明，该方法能够有效降低跨时钟域设计的验证难度和系统芯片的设计复杂度，并且不会明显增加功能部件的传输延迟和面积开销。

关键词: 系统芯片, 跨时钟域设计, 验证复杂度, 通信接口

Abstract:

Existing methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from functional design and transmits all the CDC signals in an IP design with the help of an independent and dedicated CDC processing module.It also scaled down the total number of CDC signals to two groups of opposite directions through encapsulating point-to-point communication interface as well as processing CDC signals of the same direction in combination.Experiment results demonstrate that this method is able to sharply reduce the verification complexity of CDC design and also simplify the whole SoC design,without significant adding to transfer delay or area cost of an IP design.

Key words: system-on-chip, clock domain crossing design, verification complexity, communication interface

刘丹,冯毅,党向磊,佟冬,程旭,王克义. 降低系统芯片中跨时钟域设计和验证复杂度的方法[J]. 通信学报, 2012, 33(11): 151-158.

Dan LIU,Yi FENG,Xiang-lei DANG,Dong TONG,Xu CHENG,Ke-yi WANG. Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips[J]. Journal on Communications, 2012, 33(11): 151-158.

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参考文献 20

[1]	BJERREGAARD T , MAHADEVAN S . A survey of research and practices of network-on-chip[J]. ACM Computing Surveys, 2006,38(1): 1-51.
[2]	SALEH R,WILTON S , MIRABBASI S , et a l . System-on-chip:reuse and integration[J]. Proceedings of the IEEE, 2006,94(6): 1050-1069.
[3]	TEEHAN P , GREENSTREET M , LEMIEUX G . A survey and taxonomy of GALS design styles[J]. IEEE Design and Test of Computers, 2007,24(5): 418-428.
[4]	DIKE C , BURTON E . Miller and noise effects in a synchronizing flip-flop[J]. IEEE Journal of Solid-State Circuits, 1999,34(6): 849-855.
[5]	MESSERSCHMITT D G . Synchronization in digital systems design[J]. IEEE Journal on Selected Areas in Communication, 1990,4(4): 1404-1419.
[6]	CHELCEA T , STEVEN M,NOWICK . Robust interfaces for mixed-timing systems[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004,12(8): 857-873.
[7]	JERRAYA A A , WOLF W . Multiprocessor Systems-on-Chip[M]. San Francisco: Morgan Kaufmann PublishersPress, 2005. 187-222.
[8]	STEIN M . Crossing the abyss:asynchronous signals in a synchronous world[J]. EDN, 2003. 59-69.
[9]	YU M Y,ZHANG Q L , WANG J X , et a l . The design of AMBA AHB/VCI wrapper[A]. Proceedings of 5th International Conference on ASIC[C]. Beijing,China, 2003. 438-442.
[10]	HWANG Y T , LIN S C . Automatic protocol translation and template based interface synthesis for IP reuse in SoC[A]. IEEE Asia-Pacific Conference on Circuits and Systems[C]. Taiwan,China, 2004. 565-568.
[11]	GINOSAR R . Fourteen ways to fool your synchronizer[A]. Proceedings of Asynchronous Circuits and Systems (ASYNC)[C]. Van Couver,BC,Canada, 2003. 89-91.
[12]	BIRNBAUM M . Essential Electronic Design Automation (EDA)[M]. London: Prentice Hall PTRPress, 2004.
[13]	FENG Y , ZHOU Z , TONG D ,et al. Clock domain crossing fault model and coverage metrics for validation of SoC design[A]. Design,Automation ＆ Test in Europe Conference ＆ Exhibition (DATE)[C]. Nice Acropolis,France, 2007. 1385-1390.
[14]	冯毅, 易江芳, 刘丹 ,等. 面向SoC系统芯片中跨时钟域设计的模型检验方法[J]. 电子学报, 2008,36(5): 1-7. FENG Y , YI J F , LIU D ,et al. Model checking on clock domain crossing design of system-on-chip[J]. Acta Electronica Sinica, 2008,36(5): 1-7.
[15]	DRECHSLER R . Advanced Formal Verification[M]. Kluwer Academic Publishers, 2004.
[16]	BENINI L , BERTOZZI D . Network-on-chip architectures and design methods[J]. IEE Proc-Comput Digit Tech, 2005,152(2): 261-272.
[17]	LINES A . Asynchronous interconnect for synchronous SoC design[J]. IEEE Micro, 2004,24(1): 32-41.
[18]	程旭, 陆俊林, 易江芳 ,等. 面向 UMPC的北大众志-SK 系统芯片[J]. 计算机学报, 2008,31(11): 1877-1887. CHENG X,LU J L , YI J F , et a l . Architecture for PKUnity-SK SoC for UMPC[J]. Chinese Journal of Computers, 2008,31(11): 1877-1887.
[19]	Virtual component interface standard[EB/OL]. , 2001.
[20]	GROSS D , CARL M H . Fundamentals of Queuing Theory[M]. Wiley, 1998.

设计	传统通信接口部件	SEC通信接口部件
设计	传统通信接口部件	通信接口转换	IP复用逻辑
	P2P接口控制	P2P接口控制	统一接口控制
功能设计	通信接口控制	统一接口控制	通信接口控制
功能设计	P2P 接口与通信接口转换	统一接口与 P2P接口转换	通信接口与统一接口转换
CDC设计	多组CDC信号的处理		FIFO处理2组CDC信号
CDC设计	CDC 处理的控制和CDC信号状态的判断		发送状态机接收状态机

交易长度	交易间隔	SFIFO深度	FIFO总量减少	面积开销/μm²	面积增加
1	57	/	/	/	/
4	226	15	13.22%	428 506	-0.03%
8	452	18	4.33%	430 250	0.38%
16	904	34	-43.11%	456 514	6.51%

降低系统芯片中跨时钟域设计和验证复杂度的方法

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

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