基于演化硬件的硬件重构编码方案及演化算法研究

doi:1000-436X(2012)08-0035-07

通信学报 ›› 2012, Vol. 33 ›› Issue (8): 35-41.doi: 1000-436X(2012)08-0035-07

基于演化硬件的硬件重构编码方案及演化算法研究

王婷,兰巨龙,邬钧霆

国家数字交换系统工程技术研究中心，河南郑州450002

出版日期:2012-08-25 发布日期:2017-08-02
基金资助:
国家重点基础发展计划（“973”计划）基金资助项目;国家重点基础发展计划（“973”计划）基金资助项目

Hardware reconfigurable coding and evolution algorithm based on evolvable hardware

Ting WANG,Ju-long LAN,Jun-ting WU

National Digital Switching System Engineering＆Technology Research Center,Zhengzhou 450002 China

Online:2012-08-25 Published:2017-08-02
Supported by:
The National Basic Research Program of China(973 Program);The National Basic Research Program of China(973 Program)

摘要/Abstract

摘要：

基于柔性网络技术背景，面向SRAM结构的FPGA平台，提出一种基于LUT(look up table)结构的二维映射函数增量染色体编码方案（PMFICC,planar mapped function increments chromosome coding），该方案利用二进制配置文件串双平面映射方式进行编码变换，可有效提高硬件的重构效率。同时在该方案的基础上引入局部优化机制，提出一种改进的差分演化（MDE,modified differential evolution）算法，该算法可有效提高收敛速度和全局优化效率。最后对该算法进行了仿真验证，结果表明：MDE算法改进了差分演化算法容易陷入局部最优的不足，可以更加逼近实际最优解。

关键词: 演化硬件, 硬件重构, 染色体编码, 元素图, 差分演化

Abstract:

A planar mapping function increments chromosome coding method based on FPGA platform with SRAM-architecture was proposed.The method could improve hardware reconfiguration efficiency by coding mapping realized by double platform mapping of binary configurable file string.Meanwhile,a betterment difference evolution algorithm was proposed based on local optimal mechanism introduced.The algorithm could promote convergence rate and whole efficiency.Finally,the result of the algorithm emulation shows that:MDE improves disadvantage of difference evolution algorithm with local optimal and approaches actual optimization outcome.

Key words: evolvable hardware, hardware reconfiguration, chromosome coding, element graph, difference evolution

王婷,兰巨龙,邬钧霆. 基于演化硬件的硬件重构编码方案及演化算法研究[J]. 通信学报, 2012, 33(8): 35-41.

Ting WANG,Ju-long LAN,Jun-ting WU. Hardware reconfigurable coding and evolution algorithm based on evolvable hardware[J]. Journal on Communications, 2012, 33(8): 35-41.

图/表 8

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参考文献 18

[1]	姚爱红，张国印，关琳．基于动态可重构FPGA的自演化硬件概述[J]. 智能系统学报， 2008,3(5):436-440. YAO A H , ZHANG G Y , GUAN L . A survey of dynamically and partially reconfigurable FPGA-based self-evolvable hardware[J]. CAAI Transactions on Intelligent Systems, 2008,3(5):436-440.
[2]	兰巨龙．可重构信息通信基础网络体系研究．国家重点基础研究发展计划（973计划）项目计划任务书[R]. 2011. LAN J L . Reconfigurable Basic Network of Information and Communication System[R]. National Key Basic Research and Development Program Project planTask(973 Project)[R]. 2011.
[3]	李玉峰，邱菡，兰巨龙．可重构路由器研究的现状与展望[J]．中国工程科学， 2008,10(7):83-87. LI Y F , QIU H , LAN J L . The study of reconfigurable router status and prospect[J]. China Engineering Science, 2008,10(7):83-87.
[4]	姚睿，于盛林，王友仁等．采用主流FPGA的数字电路在线生长进化方法[J]．南京航空航天大学学报， 2007,39(5):583-585. YAO R , YU S , WANG Y R , et al. Online growing evolution and evaluation approach based on mainstream FPGA[J]. Journal of Nanjing University of Aeronautics ＆ Astronautics, 2007,39(5):583-585.
[5]	KAUFMANN P , PLESSL C , PLATZNER M . Evocaches:application-specific adaptation of cache mappings[A]. NASA/ESA Conference on Adaptive Hardware and Systems[C]. 2009. 13-17.
[6]	YANG H Q , CHEN L G , LIU S T , et al. A flexible bit-stream level evolvable hardware platform based on FPGA[A]. NASA/ESA Conference on Adaptive Hardware and Systems[C]. 2009. 51-58.
[7]	LOHN J , HORNBY C . Evolvable hardware:using evolutionary computation to design and optimize hardware systems[J]. IEEE Computational Intelligence Magazine, 2006,1(1): 19-27.
[8]	MAO N , MINORU W . A sixteen-context dynamic optically reconfigurable gate array[A]. NASA/ESA Conference on Adaptive Hardware and Systems[C]. 2009. 121-125.
[9]	SHANG L H , ZHOU M , et al. A new application-tuned processor architecture for high-performance reconfigurable computing[A]. NASA/ESA Conference on Adaptive Hardware and Systems[C]. 2009. 139-145.
[10]	李敏强，寇纪淞，林丹等．遗传算法的基本理论与应用[M]．北京：科学出版社， 2002. LI M Q , KOU J S , LIN D , et al. Genetic Algorithm is the Basic Theory and the Application[M]. Beijing: Science Press, 2002.
[11]	XILINX I.Virtex-II platform FPGA user guide[EB/OL]. .
[12]	AROSTEGUI M , SANCHEZ E , CABESTANY J . An in-system routing strategy for evolvable hardware programmable platforms[A]. Proc of the 3rd NASA/DoD,Long Beach[C]. 2001. 157-166.
[13]	OREIFEJ R , AIHADDAD R , HENG T , et al. Layered approach to intrinsic evolvable hardware using direct bit-stream manipulation of virtex-II prodevices[A]. International Conference on Field Programmable Logic and Applications(FPL 2007)[C]. Amsterdam, 2007. 299-304.
[14]	MUSRRAT A , PANT M , ABRAHAM A . Simplex differential evolution[J]. Acta Polytechnica Hungarica, 2009,6(5): 95-102.
[15]	MUSRRAT A , PANT M , et al. A modified differential evolution algorithm and its application to engineering problems[A]. International Conference of Soft Computing and Pattern Recognition[C]. 2009. 196-200.
[16]	YANG Z Y , TANG K , YAO X . Large scale evolutionary optimization using cooperative coevolution[A]. Information Sciences[C]. 2008. 2986-2991.
[17]	XILINX C.XILINX development system reference guide 8.li[EB/OL]. ,Xilinx data sheet, 2007.
[18]	XILINX C.XAPP290:two flows for partial reconfiguration: module based or difference based[EB/OL]. , 2004.

x	f(x)
000	a
001	b
010	c
011	d
100	e
101	f
110	g
111	h

函数1		函数2
DE	MDE	DE	MDE
?78.326 1	?78.332 1	?0.996	?0.998
?78.332 6	?78.333 8	?0.998	?0.998
?78.332 1	?78.332 3	?0.998	?0.997
?32.296 3	?78.332 8	?0.325	?0.994
?78.338 1	?78.329 9	?0.991	?0.998
?78.332 6	?78.332 2	?0.995	?0.996

基于演化硬件的硬件重构编码方案及演化算法研究

Hardware reconfigurable coding and evolution algorithm based on evolvable hardware

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