[1] |
李玉峰, 邱菡, 兰巨龙 . 可重构路由器研究的现状与展望[J]. 中国工程科学, 2008,10(7):82-89. LI Y F , QIU H , LAN J L . Status quo and outlook of reconfigurable research[J]. Engneering Science, 2008,10(7):82-89.
|
[2] |
HU C C , WU C , X W , et al. On the design of green reconfigurable router toward energy efficient internet[J]. IEEE Communications Magazine, 2011,49(6): 83-87.
|
[3] |
龚正虎, 傅彬, 卢泽新 . 软件集群路由器体系结构研究[J]. 国防科学技术大学学报, 2006,28(3):40-43. GONG Z H , FU B , LU Z X . Research on the architecture of software based cluster routers[J]. Journal of National University of Dependence Technology, 2006,28(3):40-43.
|
[4] |
LEE D C , MIDKIFF S F . Reconfigurable routers:a new paradigm for switching device architecture[EB/OL]. , 1998.
|
[5] |
KOHLER E , MORRIS R , CHEN B , et al. The click modular router[A]. Proceedings of the ACM Symposium on Operating Systems Principles(SOSP)[C]. 1999. 217-231.
|
[6] |
DAN D , ZUBIN D , GURU P , et al. Router plugins:a software architecture for next generation routers[A]. Proc of ACM SIGCOMM[C]. 1998. 229-240.
|
[7] |
HAN S , JANG K , PARK K , et al. Packet shader:a GPU-accelerated software router[A]. ACM SIGCOMM[C]. New Delhi,India, 2010. 195-206.
|
[8] |
LEE D , HARPER S , ATHANAS P , et al. A stream-based reconfigurable router prototype[A]. IEEE International Conference on Communications[C]. Vancouver,BC, 1999. 581-585.
|
[9] |
LOCKWOOD J , NAUFEL N , TURNER J , et al. Reprogrammable network packet processing on the field programmable port extender(FPX)[A]. ACM International Symposium on Field Programmable Gate Arrays(FPGA)[C]. Monterey,CA,USA, 2001. 87-93.
|
[10] |
NAOUS J , GIBB G , BOLOUKI S , et al. NetFPGA:reusable router architecture for experimental research[A]. Proceedings of the ACM Workshop on Programmable Routers for Extensible Services of Tomorrow(PRESTO'08)[C]. New York,NY,USA, 2008. 1-7.
|
[11] |
ANWER B , TARIQ M , MOTIWALA M , et al. Switch blade:a platform for rapid deployment of network protocols on programmable hardware[A]. Proceedings of the ACM SIGCOMM 2010[C]. New Delhi,India, 2010. 183-194.
|
[12] |
KURT K , SHARAD M , RICHARD A . From ASIC to ASIP:the next design discontinuity[A]. International Conference on Computer Design[C]. 2002. 84-90.
|
[13] |
LIU D , HUA B , HU X , et al. High-performance packet classification algorithm for many-core and multithreaded network processor[A]. Proc of the 6th IEEE International Conference on CASES[C]. 2006.
|
[14] |
FRANKE H , XENIDIS J , BASSO C , et al. Introduction to the wire-speed processor and architecture[J]. IBM Journal of Research and Development, 2010,54(1): 27-37.
|
[15] |
SEDA O , MEMIK G , WILLIAM H , et al. Design and analysis of a layer seven network processor accelerator using reconfigurable logic[A]. IEEE Symposium on Field-programmable Custom Computing Machines[C]. Napa Valley,CA, 2002.
|
[16] |
ALBRECHT C , FOAG J , KOCH R , et al. DynaCORE–a dynamically reconfigurable coprocessor architecture for network processors[A]. Proc of the Euromicro Conference on Parallel,Distributed and Network-centric Processing[C]. 2006.
|
[17] |
BHUGRA H , CHAPMAN D . Look-Aside(LA-1)Interface Implementation Agreement[S]. 2004.
|
[18] |
NetLogic Corp. XLR 732 datsheet[EB/OL]. .
|
[19] |
陈一骄, 卢泽新, 孙志刚 . 基于FPGA的可重构硬件实现技术研究[J]. 信息工程大学学报, 2009,10(1):94-97. CHEN Y J , LU Z X , SUN Z G . Implementation research of reconfigurable hardware based-on FPGA[J]. Journal of Information Engineering University, 2009,10(1):94-97.
|