基于FPGA的部分并行QC-LDPC译码器高效存储方法

doi:10.3969/j.issn.1000-436x.2012.11.021

Journal on Communications ›› 2012, Vol. 33 ›› Issue (11): 165-170.doi: 10.3969/j.issn.1000-436x.2012.11.021

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Efficient storage method for FPGA-based partially parallel QC-LDPC decoder

Rui-jia YUAN^1,²,Bao-ming BAI^1,²

¹ State Key Lab of Integrated Services Networks,Xidian University,Xi’an 710071,China
² Science and Technology on Information Transmission and Dissemination in Communication Networks Lab,CETC No.54 Research Institute,Shijiazhuang 050002,China

Online:2012-11-25 Published:2017-07-25
Supported by:
The National Basic Research Program of China (973 Program);The National Natural Science Foundation of China;The National S＆T Major Project of China;Science and Technology on Information Transmission and Dissemination in Communication Networks Laboratory

Abstract

Abstract:

An efficient storage method of hard decisions sharing intrinsic and extrinsic memory banks for partially parallel QC-LDPC decoder was proposed.Extra memory banks for storing hard decisions were avoided in this method,which result in significantly reduced consumption of RAM resources and routed complexity.Implementation results based on a Xilinx XC2V6 000-5ff1 152 FPGA show that the proposed method improves the frequency and decodes throughput of the system,and significantly reduced the requirements for the number of BRAM.

Key words: LDPC code, decoder, partially parallel, efficient storage, FPGA implementation

Rui-jia YUAN,Bao-ming BAI. Efficient storage method for FPGA-based partially parallel QC-LDPC decoder[J]. Journal on Communications, 2012, 33(11): 165-170.

Figures/Tables 4

References 11

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存储方法	slice	F/F	LUT	Block RAM	关键路径时延/ns	吞吐量/(Mbit·s^-1)
文献[8]的方法	1 477	1 012	2 648	36	6.802	58.8
本文提出方法	1 485	1 682	2 050	24	4.739	84.4

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Efficient storage method for FPGA-based partially parallel QC-LDPC decoder

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