基于FPGA的新型强弱混合型PUF电路设计

doi:10.11959/j.issn.2096-109x.2021028

Abstract

Abstract:

Physically unclonable function (PUF) can produce intrinsic keys with characteristics of randomness, uniqueness and tamper-proof by exploiting the process deviations which can not be avoided in the chip manufacturing process.A novel hybrid strong and weak PUF (SWPUF) circuit design based on field-programmable gate array(FPGA) was proposed after the investigation of the PUF circuit structures and principles.To address the limitation of designing strong-PUF and weak-PUF discretely, SWPUF could be configured into two topologies conveniently depending on the Hamming Weight (HW) of the challenges.In addition, the statistical characteristics of the responses could be further improved by a XOR-decorrelation technique.The proposed SWPUF was implemented on a Xilinx Artix-7 FPGA (28nm technology), and a self-built test platform was set up by using Matlab and MicroBlaze microcontroller.Experimental results show that the SWPUF has good performances of randomness (96.98%), uniqueness (99.64%) and reliability (96.6%).Logic register analysis also shows that the SWPUF has a better anti-attack capability than the traditional Arbiter-PUF in the case of with small HW, and can be used in the information security, such as key storage (especially to weak PUF) and device authentication (especially to strong PUF).

Key words: hybrid strong and weak, physically unclonable function, FPGA, circuit design

CLC Number:

TP309

Jiana LIAN, Pengjun WANG, Gang LI, Xuejiao MA, Guanbao ZHAI. Novel hybrid strong and weak PUF design based on FPGA[J]. Chinese Journal of Network and Information Security, 2021, 7(2): 94-103.

Figures/Tables 16

激励	C₀	C₁	C₂	C₃	…	C_n
激励1	1	0	0	0	…	0
激励2	0	1	0	0	…	0
激励3	0	0	1	0	…	0
激励4	0	0	0	1	…	0
$⋮$	$⋮$	$⋮$	$⋮$	$⋮$	…	$⋮$
激励N	0	0	0	0	…	1

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时钟脉冲	输入序列值	状态S（初值为0101）				输出R
时钟脉冲	输入序列值	a₁	a₂	a₃	a₄	输出R
1	1	1	0	1	1	1
2	0	0	1	1	0	0
3	0	1	1	0	0	0
4	1	1	0	0	1	0
5	0	0	0	0	1	0
6	1	1	0	1	0	1
7	1	1	1	0	1	1
8	0	0	0	1	1	0

移位寄存器位数n	异或间隔位数
移位寄存器位数n	0	1	2	3
4	46.94%	41.53%	—	—
6	49.65%	47.25%	50.82%	—
8	51.84%	48.48%	38.62%	38.52%
10	49.97%	49.67%	38.64%	38.62%
12	50.14%	50.29%	49.65%	49.89%
14	49.06%	48.91%	38.55%	38.64%
16	50.16%	50.11%	48.81%	50.07%
18	51.92%	51.29%	50.64%	38.65%
20	50.74%	50.15%	38.74%	50.81%

对比文献	随机性	唯一性	可靠性	响应位数	实现方式	工艺/nm
Racing APUF^[30]	92.6%	—	91.6%	—	FPGA	65
multi-line APUF^[31]	99.4%	93%	99.9%	64	FPGA	65
APUF^[32]	90.4%	92.8%	99.3%	64	FPGA	65
DAPUF^[32]	91.4%	82.6%	90.2%	64	FPGA	65
XRBR PUF^[33]	—	81.34%	98.22%	—	FPGA	45
XRRO PUF^[33]	—	97.52%	97.72%	—	FPGA	45
RO PUF^[18]	84.58%	96.02%	98.25%	1024	FPGA	28
Zhang PUF^[34]	89.8%	99.2%	96.3%	64	FPGA	28
基于延迟的PUF^[35]	90.8%	99.4%	96.8%	64	FPGA	28
FF-APUF^[36]	80%	83.06%	97.1%	64	FPGA	28
本文所提SWPUF	96.98%	99.64%	96.6%	256	FPGA	28
注：“—”表示无法获得。

Novel hybrid strong and weak PUF design based on FPGA

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