SM3杂凑算法的SoPC组件实现

doi:10.11959/j.issn.2096-109x.2017.00146

Abstract

Abstract:

Firstly the realization of SM3 on SoC was given.The structure of the algorithm was analyzed mainly,and the algorithm was realized by the Verilog hardware description language,in order to simulate this algorithm,the Altera simulation software ModelSim was chosen,SoPC Builder was used for interface package,and finally it was implemented in the Cyclone IV EP4CE22F17C8N.Its operation frequency can reach 165 MHz and its throughput rate is 1 184.8 Mbit/s.

Key words: SM3, FPGA, hardware implementation, SoC

CLC Number:

TP393

Meng-li SHAO,Xin-chun YIN,Yan-mei LI. Implementation of SM3 algorithm based on SoPC component[J]. Chinese Journal of Network and Information Security, 2017, 3(5): 47-53.

Figures/Tables 10

References 17

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接口名称	接口类型	接口功能说明
clk	input wire	时钟输入，1 bit
reset	input wire	模块置位，1 bit
div_address	input wire[5:0]	读取和存储数据单元的地址
div_chipselect	input wire	模块运行选择使能接口
div_writedata	input wire[31:0]	可以根据地址向模块中写相应的数据，如消息分组
div_readdata	output wire[31:0]	读取运行结果或运行结束标志
div_irq	output wire	压缩完成时，发出中断请求

地址类型	偏移量	说明
写地址	偏移量0~15	存放分组信息(第31~0位)
写地址	偏移量16	Start信号寄存器，用于产生使能脉冲(第0位)
写地址	偏移量17	Fenzu 信号寄存器，用于确定 CF数据的初始化(第0位)
写地址	偏移量18	done_tick信号寄存器，虚拟数据，用于清除done_tick标记(第0位)
读地址	偏移量19~26	分组压缩信息寄存器(第31~0位)
读地址	偏移量27	ready信号寄存器(第0位)
读地址	偏移量18	done_tick信号寄存器(第0位)

宏变量	说明
#define DATA_IN_OFT 0	分组信息首地址
#define START_REG_OFT 16	start信号地址
#define FENZU_REG_OFT 17	fenzu信号地址
#define DATA_OUT_OFT 19	分组压缩信息首地址
#define READY_OFT 27	ready信号寄存地址
#define DONE_REG_OFT 18	done_tick信号寄存地址

文献	器件	资源	频率（MHz）	吞吐率/(Mbit·s^?1）
文献[1]	V2	1035(Slices)	105.7	795
文献[1]	V2P	1035(Slices)	124.6	938
文献[1]	Virtex-5	328(Slices)	197.2	1 483
文献[2]	EP2S90F1508C3	1244(ALUTS)	131	474.21
文献[2]	EP2S90F1508C3	1936(ALUTS)	68.86	526.21
文献[12]	—	76300(LE)	191	75 304
文献[13]	EPC20F324C6	1789(LE)	92.55	724.40
文献[14]	—	—	125	32 768
本文	EP4CE22F17C8	3933(LE)	165	1 184.8

Implementation of SM3 algorithm based on SoPC component

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