面向双线性对的  F   p 2   -FIOS模乘算法及其实现架构研究

doi:10.11959/j.issn.1000-436x.2022040

Abstract

Abstract:

A quadratic extended-domain finely integrated operand scanning ( $F_{p^{2}}$ -FIOS) modular multiplication algorithm for bilinear pairs was proposed to address the problem of low efficiency of bilinear pair operations.The algorithm effectively reduced the number of modular reductions in modular multiplication by optimizing the operation process of (AB+CD)mod P under the quadratic expansion domain.Two hardware architectures and their scheduling methods were designed to meet different application requirements.In order to improve the computational efficiency of the algorithm, the TSMC 55 nm process was used to realize the bilinear pairing operation unit.Compared with the existing literature, the designed architecture is superior to similar modular multiplication designs in performance indicators such as the first modular multiplication time, clock frequency and the area-time product, and also has certain advantages in the overall Optimal ate pair implementation.

Key words: bilinear pair, extended domain, modular multiplication, hardware implementation architecture

CLC Number:

TN918

Zhanpeng JIANG, Mingwei SUN, Hai HUANG, Jiang XU, Zhiwei LIU, Rui BAI, Zhou FANG, Jiaxing QU. Research on $F_{p^{2}}$ -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture[J]. Journal on Communications, 2022, 43(2): 100-108.

Figures/Tables 8

算法	乘法	加法
FIOS	4n²+2n	10n²+8n+4
高基蒙哥马利模乘	4n²+2n	8n²+6n+4
$F_{p^{2}} -FIOS$	3n²+n	6n²+2n+2

相关设计	工艺库	乘法运算/bit	乘法器数量/个	频率	周期/个	时间/ns	等效门数/K	AT
文献[10]	TSMC 65 nm	53×320	3	800 MHz	18	22.5	215	4 837.5
文献[11]	SMIC 65 nm	24×256	3	709 MHz	50	70	226	15 820
文献[14]	TSMC 55 nm	64×64	4	1.3 GHz	31	23.87	192	4 583
$F_{p^{2}}$ -FIOS2（本文）	TSMC 55 nm	64×64	2	2.00 GHz	31	15.5	110	1 705
	TSMC 55 nm	32×32	2	1.82 GHz	107	58.85	60	3 531
	TSMC 55 nm	64×64	3	2.00 GHz	24	12.0	139	1 668
$F_{p^{2}}$ -FIOS3（本文）	TSMC 55 nm	32×32	3	1.82 GHz	76	41.8	68	2 842.4
	TSMC 55 nm	16×16	3	1.89 GHz	276	146.28	52	7 606.56
	TSMC 55 nm	8×8	3	1.96 GHz	1060	540.6	45	2 4327

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相关设计	工艺库	频率/MHz	周期/个	时间/ms	面积
文献[10]	TSMC 65 nm	800	350 740	0.521	323K Gates
文献[14]	Xilinx FPGA Virtex-7	115	394 806	3.43	28K Slices, 128 DSPs
文献[15]	Xilinx FPGA Virtex-6	125	283 111	2.26	4380 Slices, 131DSPs
文献[16]	Xilinx FPGA Virtex-6	165	143 111	0.573	7032 Slices, 32DSPs, 45BRAM
文献[17]	Xilinx FPGA Virtex-6	156	208 000	1.33	3072 Slices, 36DSPs, 18BRAM
文献[18]	Xilinx FPGA Virtex-7	181	2 552 346	14.14	2506 Slices, 40DSPs, 20BRAM
本文架构	TSMC 55 nm	500	97 824	0.186	850K Gates

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Research on F p 2 -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture

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Research on $F_{p^{2}}$ -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture