Abstract:

Aiming at the problem that it is difficult for existing implementation algorithms of symbol timing recovery to give full consideration to high convergence accuracy and the robustness to resist timing deviation, a high-speed parallel symbol timing recovery algorithm with resampling was proposed.The timing frequency offset and timing phase offset were corrected by using double feedback loops.In the design of parallel resampling, the implementation of parallel numerically controlled oscillators and the use of enable signals sorting and shift registers to implement data reordering were proposed.When designing the timing recovery loop, the parallel implementation structure of the O＆amp;M timing error estimation algorithm was analyzed and deduced, and the design method and implementation structure of the loop correction were proposed based on the analysis of the timing phase/frequency offset correction principle.The FPGA test results show that the proposed algorithm can realize the symbol timing recovery of 64APSK modulated signals with arbitrary multiple symbol rate between 4 and 16 times, and the error vector magnitude (EVM) with the ideal signal is within 4%, which meets the requirements of broadband satellite communication.

Key words: broadband satellite communication, STR, dual feedback, parallel implementation