[1] |
BJERREGAARD T , MAHADEVAN S . A survey of research and practices of network-on-chip[J]. ACM Computing Surveys, 2006,38(1): 1-51.
|
[2] |
SALEH R,WILTON S , MIRABBASI S , et a l . System-on-chip:reuse and integration[J]. Proceedings of the IEEE, 2006,94(6): 1050-1069.
|
[3] |
TEEHAN P , GREENSTREET M , LEMIEUX G . A survey and taxonomy of GALS design styles[J]. IEEE Design and Test of Computers, 2007,24(5): 418-428.
|
[4] |
DIKE C , BURTON E . Miller and noise effects in a synchronizing flip-flop[J]. IEEE Journal of Solid-State Circuits, 1999,34(6): 849-855.
|
[5] |
MESSERSCHMITT D G . Synchronization in digital systems design[J]. IEEE Journal on Selected Areas in Communication, 1990,4(4): 1404-1419.
|
[6] |
CHELCEA T , STEVEN M,NOWICK . Robust interfaces for mixed-timing systems[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004,12(8): 857-873.
|
[7] |
JERRAYA A A , WOLF W . Multiprocessor Systems-on-Chip[M]. San Francisco: Morgan Kaufmann PublishersPress, 2005. 187-222.
|
[8] |
STEIN M . Crossing the abyss:asynchronous signals in a synchronous world[J]. EDN, 2003. 59-69.
|
[9] |
YU M Y,ZHANG Q L , WANG J X , et a l . The design of AMBA AHB/VCI wrapper[A]. Proceedings of 5th International Conference on ASIC[C]. Beijing,China, 2003. 438-442.
|
[10] |
HWANG Y T , LIN S C . Automatic protocol translation and template based interface synthesis for IP reuse in SoC[A]. IEEE Asia-Pacific Conference on Circuits and Systems[C]. Taiwan,China, 2004. 565-568.
|
[11] |
GINOSAR R . Fourteen ways to fool your synchronizer[A]. Proceedings of Asynchronous Circuits and Systems (ASYNC)[C]. Van Couver,BC,Canada, 2003. 89-91.
|
[12] |
BIRNBAUM M . Essential Electronic Design Automation (EDA)[M]. London: Prentice Hall PTRPress, 2004.
|
[13] |
FENG Y , ZHOU Z , TONG D ,et al. Clock domain crossing fault model and coverage metrics for validation of SoC design[A]. Design,Automation & Test in Europe Conference & Exhibition (DATE)[C]. Nice Acropolis,France, 2007. 1385-1390.
|
[14] |
冯毅, 易江芳, 刘丹 ,等. 面向SoC系统芯片中跨时钟域设计的模型检验方法[J]. 电子学报, 2008,36(5): 1-7. FENG Y , YI J F , LIU D ,et al. Model checking on clock domain crossing design of system-on-chip[J]. Acta Electronica Sinica, 2008,36(5): 1-7.
|
[15] |
DRECHSLER R . Advanced Formal Verification[M]. Kluwer Academic Publishers, 2004.
|
[16] |
BENINI L , BERTOZZI D . Network-on-chip architectures and design methods[J]. IEE Proc-Comput Digit Tech, 2005,152(2): 261-272.
|
[17] |
LINES A . Asynchronous interconnect for synchronous SoC design[J]. IEEE Micro, 2004,24(1): 32-41.
|
[18] |
程旭, 陆俊林, 易江芳 ,等. 面向 UMPC的北大众志-SK 系统芯片[J]. 计算机学报, 2008,31(11): 1877-1887. CHENG X,LU J L , YI J F , et a l . Architecture for PKUnity-SK SoC for UMPC[J]. Chinese Journal of Computers, 2008,31(11): 1877-1887.
|
[19] |
Virtual component interface standard[EB/OL]. , 2001.
|
[20] |
GROSS D , CARL M H . Fundamentals of Queuing Theory[M]. Wiley, 1998.
|