Abstract: To solve the contradiction between the memory requirement and the inspection performance, a matching engine with two-stage memory was proposed for the first time. To deploy the state table to two-stage memory, theories of Markov chain was applied to the FSA. By computing the steady vector, the random access probabilities of each state could be obtained. Further, the states with higher probabilities were deployed in the embedded memory of FPGA, and the states with lower probabilities were deployed in SRAM. Rules in L7-filter were tested in simulation experiments, and the results show that our method can reach a throughput of 33 Gbit/s in large scale FSA, which is 50 times than that of arranging the whole state table in SRAM.