[1] |
SINGH K , TIWARI S C , GUPTA M . A closed-loop ASIC design approach based on logical effort theory and artificial neural networks[J]. Integration, 2019,69: 10-22.
|
[2] |
LIU Z , DOU Y , JIANG J ,et al. An FPGA-based processor for training convolutional neural networks[C]// International Conference on Field Programmable Technology (ICFPT). 2018.
|
[3] |
方睿, 刘加贺, 薛志辉 ,等. 卷积神经网络的 FPGA 并行加速方案设计[J]. 计算机工程与应用, 2015,51(8): 32-36.
|
|
FANG R , LIU J H , XUE Z H ,et al. FPGA-based design for convolution neural network[J]. Computer Engineering and Applications, 2015,51(8): 32-36.
|
[4] |
王巍, 周凯利, 王伊昌 ,等. 卷积神经网络(CNN)算法的 FPGA并行结构设计[J]. 微电子学与计算机, 2019,36(4): 57-62,66.
|
|
WANG W , ZHOU K L , WANG Y C ,et al. FPGA parallel structure design of convolutional neural network(CNN) algorithm[J]. Microelectronics & Computer, 2019,36(4): 57-62.
|
[5] |
翟社平, 邱程, 杨媛媛 ,等. 基于 FPGA 的卷积神经网络加速器设计与实现[J]. 微电子学与计算机, 2019,36(8): 83-86.
|
|
ZHAI S P , QIU C , YANG Y Y ,et al. Design and implementation of convolutional neural network accelerator based on FPGA[J]. Microelectronics & Computer, 2019,36(8): 83-86.
|
[6] |
窦阳, 卿粼波, 何小海 ,等. 基于FPGA的CNN加速器设计与实现[J]. 信息技术与网络安全, 2019,38(11): 96-101.
|
|
DOU Y , QING L B , HE X H ,et al. Design and implementation of CNN accelerator based on FPGA[J]. Information Technology and Network Security, 2019,38(11): 96-101.
|
[7] |
周瑛, 张铃 . 模糊集方法在检索评价系统中的应用[J]. 计算机技术与发展, 2007,17(1): 111-113.
|
|
ZHOU Y , ZHANG L . Application of fuzzy measure in information retrieval evaluation[J]. Computer Technology and Development, 2007,17(1): 111-113.
|
[8] |
VENUGOPAL S , CASTRO-PAREJA C R , DANDEKAR O S . An FPGA-based 3D image processor with median and convolution filters for real-time applications[C]// Proc of Spie-is&t Electronic Imaging. 2005.
|
[9] |
CHEN J , PRODIC A , ERICKSON R W ,et al. Predictive digital current programmed control[J]. IEEE Transactions on Power Electronics, 2003,18(1): 411-419.
|
[10] |
CHELLAPILLA K , PURI S , SIMARD P . High performance convolutional neural networks for document processing[C]// 10th International Workshop on Frontiers in Handwriting Recognition. 2006.
|
[11] |
YU Y , WU C , ZHAO T ,et al. OPU:an FPGA-based overlay processor for convolutional neural networks[J]. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 2019,28(1): 35-47.
|
[12] |
WU D , PIGOU L , KINDERMANS P J ,et al. Deep dynamic neural networks for multimodal gesture segmentation and recognition[J]. IEEE Transactions on Pattern Analysis & Machine Intelligence, 2016,38(8): 1583-1597.
|
[13] |
仇越, 马文涛, 柴志雷 . 一种基于FPGA的卷积神经网络加速器设计与实现[J]. 微电子学与计算机, 2018,35(8): 68-72.
|
|
QIU Y , MA W T , CHAI Z L . Design and implementation of a convolutional neural network accelerator based on FPGA[J]. Microelectronics & Computer, 2018,34(8): 68-72.
|
[14] |
刘勤让, 刘崇阳, 周俊 ,等. 基于线性脉动阵列的卷积神经网络计算优化与性能分析[J]. 网络与信息安全学报, 2018,4(2): 16-24.
|
|
LIU Q R , LIU C Y , ZHOU J ,et al. Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis[J]. Chinese Journal of Network and Information Security, 2018,4(2): 16-24.
|
[15] |
梁爽 . 可重构神经网络加速器设计关键技术研究[D]. 北京:清华大学, 2017.
|
|
LIANG S . Research on key technologies of reconfigurable neural network accelerator design[D]. Beijing:Tsinghua University, 2017.
|