一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

doi:10.11959/j.issn.1000-0801.2022023

Abstract

Abstract:

In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed, and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that, compared with the existing parallel Turbo decoder architectures, the proposed design architecture reduces the logic resource of state metrics calculation module about 50%, while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.

Key words: state measure merge calculation, Turbo code, FPGA implementation, parallel algorithm

CLC Number:

TN929

Qian ZHANG, Ming ZHAN, Jianwu ZHANG, Fulong WANG, Yunkai1 FENG, Hao TANG. Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations[J]. Telecommunications Science, 2022, 38(2): 47-58.

Figures/Tables 14

度量值类型	$y_{k}^{s}, y_{k}^{p_{1}}, y_{k}^{p_{2}}$	${\tilde{α}}_{k}, {\tilde{β}}_{k}, {\tilde{γ}}_{k}^{}$	$Λ_{apo, k}$
(q,f)	(5,3)	(10,3)	(11,3)

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设计方案	逻辑单元/个	寄存器/个	寄存器容量/bit
并行设计方案	3 044	572	10 240
本文设计的方案	1 583	396	10 060

Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

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