全维可重构的多模态网络交换芯片架构设计

doi:10.11959/j.issn.1000-0801.2023129

Abstract

Abstract:

At present, IP network has the problems of rigid structure, poor scalability and poor security.To solve these problems, the concept of polymorphic network has been proposed by researchers and gradually become a research hotspot.The programmable network switching chip is the basis of polymorphic network implementation.Therefore, a full-dimensional reconfigurable polymorphic network switching chip architecture was proposed.Based on eFPGA in the chip, the port-level and bit-level fine-grained reconfigurable polymorphic network was realized.Based on self-designed process element (PE), the coarse-grained reconfigurable network switching engine was realized.Thereby the full-dimensional reconfigurable polymorphic network switching chip was realized and laid the foundation for the data layer of polymorphic network.To improve the network switching performance, an improved bit vector algorithm was proposed, which could realize fast flow table lookup with a smaller resource consumption.The proposed algorithm has showed its practicability in the research.

Key words: switching chip, polymorphic network, reconfigurable computing

CLC Number:

TP393

Yu LI, Zhaozhao LI, Ping LYU, Qinrang LIU. Design on the full-dimensional reconfiguration polymorphic network switching chip architecture[J]. Telecommunications Science, 2023, 39(6): 22-32.

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References 16

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协议名称	LUT6 （利用率）	REG （利用率）	BRAM （利用率）
10 Gbit/s以太网MAC	892（3.4%）	428（0.8%）	0（0%）

算法	存储容量/bit	面积/mm²
ABV	294 912	0.105 636
AFBV	294 912	0.105 636
IAFBV	49 512	0.020 502

指标	性能
面积	0.102 mm²
主频	500 MHz
典型功耗	34 mW
Core电压	0.9 V
总线宽度	128 bit

Design on the full-dimensional reconfiguration polymorphic network switching chip architecture

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