Journal on Communications ›› 2020, Vol. 41 ›› Issue (12): 100-109.doi: 10.11959/j.issn.1000-436X.2020226

• Papers • Previous Articles     Next Articles

Design and implementation of high-speed scalar multiplier for multi-elliptic curve

Bin YU, Hai HUANG, Zhiwei LIU, Shilei ZHAO, Ning NA   

  1. School of Software and Microelectronics, Harbin University of Science and Technology, Harbin 150080, China
  • Revised:2020-09-17 Online:2020-12-25 Published:2020-12-01
  • Supported by:
    The Natural Science Foundation of Heilongjiang(YQ2019F010);The University Nursing Program for Young Scholars with Creative Talents in Heilongjiang(UNPYSCT-2017081);The National Key Research and Development Program of China(2018YFB2202100)

Abstract:

Aiming at the problem that the existing scalar multiplier cannot be applied to multi-elliptic curve and the cost is expensive, a high-speed scalar multiplier was designed, applicable to two types of elliptic curves over prime fields.Firstly, in terms of the scalar multiplication, secp256r1 base points were processed with the comb algorithm, and the Shamir algorithm for ordinary points, and the Montgomery ladder algorithm for Curve25519.Secondly, the operation of point addition and point doubling was optimized, and the condition of Z=1 in point addition was simplified, thereby effectively reducing the number of calculation cycles.Lastly, a fast modular reduction algorithm of Curve25519 was designed for modular multiplication.Multiplexing was an important factor in the entire designing process.A 1022K equivalent gate was selected for the 55 nm CMOS process.This allowed ordinary point scalar multiplications performed on secp256r1 and Curve25519 respectively, calculating at the speeds of 153 000 times per second and 158 000 times per second, with the speed for secp256r1 1.9 times that of the existing designed one.

Key words: ECC, scalar multiplication, fast modular reduction, hardware implementation

CLC Number: 

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